Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture

• Published in: Microelectronics and reliability Vol. 147; p. 115029
• Main Authors: Ammoura, L., Flottes, M.-L., Girard, P., Noel, J.-P., Virazel, A.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.08.2023; Elsevier
• Subjects: 8T SRAM cell; Engineering Sciences; In-Memory Computing; Micro and nanotechnologies; Microelectronics; Resistive defect analysis; Test; 8T SRAM cell; Resistive defect analysis; Test; In-Memory Computing
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2023.115029

A promising new alternative to efficiently solve the Von Neumann bottleneck problem is to adopt In-Memory Computing (IMC) architectures. Beyond the arithmetic operations, IMC architectures aim at integrating additional logic operators directly in the memory array or/and at the periphery in order to provide close computing abilities. However, they are subject to manufacturing defects in the same way as conventional memories. In this paper, a comprehensive model of a 128 × 128 bitcell array based on 28 nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive defects (open and short) injected in the read port. A hierarchical analysis allowing a thorough study of each defect has been carried in order to identify their impact in both memory and computing modes, locally on the defective bitcell as well as globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-short and resistive-open defects.