A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

• Published in: Analog integrated circuits and signal processing Vol. 56; no. 1-2; pp. 5 - 12
• Main Authors: Carbognani, Flavio, Buergin, Felix, Felber, Norbert, Kaeslin, Hubert, Fichtner, Wolfgang
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.08.2008
• Subjects: Arrays; Circuits and Systems; Digital; Dissipation; Electrical Engineering; Energy transmission; Engineering; Hearing aids; Multipliers; Signal processing; Signal,Image and Speech Processing; Transmission gates; Multiplier; Hearing aids; Low power; Switching activity; Transmission gate
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-007-9086-0

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0 µW/MHz versus 10.9 µW/MHz and more for 0.25 µm CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1 µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V dd to ground resistance, hence decreasing leakage dissipation (0.55 nW versus 0.84 nW in CSM and 0.94 nW in Wallace).