Novel Electronic Devices in Macroporous Silicon: Design of FET Transistors for Power Applications

• Published in: IEEE transactions on electron devices Vol. 58; no. 9; pp. 3065 - 3071
• Main Authors: Rodriguez, A., Vega, D., Najar, R., Pina, M.
• Format: Journal Article Publication
• Language: English
• Published: New York, NY IEEE 01.09.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D transistor; All-around gate; Applied sciences; Channels; Components electrònics; Cross-disciplinary physics: materials science; rheology; device modeling; Devices; Doping; Electronics; Enginyeria electrònica; Exact sciences and technology; FET transistors; Gates; Horizontal; JFET; JFETs; Logic gates; macroporous silicon (MpSi); Materials science; MOSFET; Performance evaluation; Physics; Porous materials; granular materials; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductor process modeling; Semiconductors; Silici; Silicon; Specific materials; surrounding gate; Transistors; Àrees temàtiques de la UPC; Voltage threshold; MOSFET; FET transistors; 3-D transistor; Cylindrical configuration; High density; Junction field effect transistor; surrounding gate; JFET; device modeling; GAA transistor; All-around gate; Porous material; Modeling; macroporous silicon (MpSi); Field effect transistor; Low voltage; Electronic component; Silicon
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2159508

In this paper, we study the application of macroporous silicon (MpSi) to the fabrication of transistors: Four different FET transistor structures are proposed using MpSi as the base material. These devices have been studied by simulation, and their characteristics are shown herein. The proposed structures include JFET, MOSFET, and trio de-like devices; in this study, we have considered both vertical and horizontal structures. For the vertical case, the proposed devices use the MpSi tubes to create the channel, filling them with a semiconductor and using the bulk silicon as a cylindrical gate all around. In contrast, for the horizontal transistors, the MpSi structure is used as the channel medium, while the conductor-filled pores serve as the controlling gate, thus obtaining a trio de-like device. The use of MpSi allows one to obtain large transistor arrays of extremely high density, thus obtaining a large amount of parallel devices in a moderate-to-small device area. Even more, pore engineering introduces a degree of freedom in the design of the transistor characteristics. We show that the proposed devices have a low threshold voltage and can support large currents. Finally, the behavior of these structures is studied for different geometries.