Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution

• Published in: Solid-state electronics Vol. 53; no. 7; pp. 735 - 740
• Main Authors: Bidal, G., Loubet, N., Fenouillet-Beranger, C., Denorme, S., Perreau, P., Fleury, D., Clement, L., Laviron, C., Leverd, F., Gouraud, P., Barnola, S., Beneyton, R., Torres, A., Duluard, C., Chapon, J.D., Orlando, B., Salvetat, T., Grosjean, M., Deloffre, E., Pantel, R., Dutartre, D., Monfray, S., Ghibaudo, G., Boeuf, F., Skotnicki, T.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Kidlington Elsevier Ltd 01.07.2009; Elsevier
• Subjects: Applied sciences; Brackets; Channels; Condensed Matter; Depletion; Devices; DIBL; Electronics; Engineering Sciences; Exact sciences and technology; Folded FET; Footprints; Fully-depleted; Micro and nanotechnologies; Microelectronics; Other; Oxides; Physics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Short-channel Effects; SON; Subthreshold slope; Transistors; Ultra thin body; Ultra thin BOX; UTB 2; Wafer orientation; Wafers; Short-channel Effects; UTB 2; SON; Fully-depleted; Ultra thin BOX; Wafer orientation; Ultra thin body; Folded FET; DIBL; Subthreshold slope; Ultrathin films; Buried layer; UTB; Oxide layer; Short channel; Faceting; Field effect transistor; Selective growth; Low-power electronics; Wafer; Silicon on nothing technology; Electrical characteristic; Planar technology
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2009.02.010

This work proposes a planar fully depleted “folded” technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance drive current on narrow devices. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide ultra thin body and buried oxide (UTB 2) devices with improved drive current I on for a given designed footprint W design when scaling the device width . We compare the fabrication and electrical behavior between 〈1 1 0〉 channel, i.e. 0°-rotated wafer, and 〈1 0 0〉 channel, i.e. 45°-rotated wafer, for the same (1 0 0) surface orientation.