A Simple Method to Identify Radiation and Annealing Biases That Lead to Worst-Case CMOS Static Ram Postirradiation Response

We illustrate a simple method to identify bias conditions that lead to worst-case postirradiation speed and timing response for SRAMs. Switching cell states between radiation and anneal should lead to maximum speed and timing degradation for many hardened designs and technologies. The greatest SRAM...

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Bibliographic Details
Published inIEEE transactions on nuclear science Vol. 34; no. 6; pp. 1408 - 1413
Main Authors Fleetwood, D. M., Dressendorfer, P. V.
Format Journal Article
LanguageEnglish
Published IEEE 01.12.1987
Subjects
Annealing
Circuit testing
Degradation
Guidelines
Laboratories
Radiation hardening
Random access memory
Single event upset
Threshold voltage
Timing
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Summary:We illustrate a simple method to identify bias conditions that lead to worst-case postirradiation speed and timing response for SRAMs. Switching cell states between radiation and anneal should lead to maximum speed and timing degradation for many hardened designs and technologies. The greatest SRAM cell imbalance is also established by these radiation and annealing conditions for the hardened and commercial parts that we have examined. These results should provide insight into the behavior of SRAMs during and after irradiation. The results should also be useful to establishing guidelines for integrated-circuit functionality testing, and SEU and dose-rate upset testing, after total-dose irradiation.
Bibliography:SourceType-Scholarly Journals-2
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ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.1987.4337489