A survey of FPGA design for AI era

• Published in: Journal of semiconductors Vol. 41; no. 2; pp. 21402 - 21407
• Main Authors: Li, Zhengjie, Zhang, Yufan, Wang, Jian, Lai, Jinmei
• Format: Journal Article
• Language: English
• Published: Chinese Institute of Electronics 01.02.2020
• Subjects: ALM; CLB; DNN; DSP; FPGA; Low-precision
• ISSN: 1674-4926; 2058-6140
• DOI: 10.1088/1674-4926/41/2/021402

FPGA is an appealing platform to accelerate DNN. We survey a range of FPGA chip designs for AI. For DSP module, one type of design is to support low-precision operation, such as 9-bit or 4-bit multiplication. The other type of design of DSP is to support floating point multiply-accumulates (MACs), which guarantee high-accuracy of DNN. For ALM (adaptive logic module) module, one type of design is to support low-precision MACs, three modifications of ALM includes extra carry chain, or 4-bit adder, or shadow multipliers which increase the density of on-chip MAC operation. The other enhancement of ALM or CLB (configurable logic block) is to support BNN (binarized neural network) which is ultra-reduced precision version of DNN. For memory modules which can store weights and activations of DNN, three types of memory are proposed which are embedded memory, in-package HBM (high bandwidth memory) and off-chip memory interfaces, such as DDR4/5. Other designs are new architecture and specialized AI engine. Xilinx ACAP in 7 nm is the first industry adaptive compute acceleration platform. Its AI engine can provide up to 8X silicon compute density. Intel AgileX in 10 nm works coherently with Intel own CPU, which increase computation performance, reduced overhead and latency.