ULPFA: A New Efficient Design of a Power-Aware Full Adder

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 57; no. 8; pp. 2066 - 2074
• Main Authors: Hassoune, Ilham, Flandre, Denis, O'Connor, Ian, Legat, Jean-Didier
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Arithmetic circuits; CMOS; CMOS logic circuits; Delay; Design engineering; Design optimization; Energy consumption; Evolution; Field programmable gate arrays; full adders; Integrated circuits; Logic; Logic circuits; Logic design; low leakage; low power; Microelectronics; Parasitic capacitance; Power consumption; Ripples; Routing; Voltage
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2008.2001367

In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch-based logic and pass-transistor logic. Evolution of the proposed cell from its original version to an ultralow-power (ULP) cell is described. Quantitative comparisons of the optimized version, namely, the ULP full adder (ULPFA), are carried out versus the BBL-PT full adder and its counterparts in two well-known and commonly used logic styles, i.e., conventional static CMOS logic and complementary pass logic (CPL), in a 0.13-μm PD SOI CMOS with a supply voltage of 1.2 V, demonstrating power delay product (PDP) and static power performance that are more than four times better than CPL design. This could lead to tremendous benefit for multiplier application. The implementation of an 8-bit ripple carry adder based on the ULPFA is finally described, and comparisons between adders based on full adders from the prior art and our ULPFA version demonstrate that our development outperforms the static CMOS and the CPL full adders, particularly in terms of power consumption and PDP by at least a factor of two.