Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption

• Published in: IEEE transactions on computers Vol. 64; no. 12; pp. 3335 - 3347
• Main Authors: Ingelsson, Urban, Goel, Sandeep Kumar, Larsson, Erik, Marinissen, Erik Jan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: abort-on- fail; abort-onfail; Computer simulation; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik; Engineering and Technology; Failure analysis; Integrated circuits; Job shop scheduling; Manufacturing processes; manufacturing test; Mathematical models; Modular; modular test; Modules; preemptive scheduling; Probability; Product testing; Reduction; reject-oriented analysis; Scheduling; stacked integrated circuit; System-on-Chip; Teknik; test scheduling; Test times; Three dimensional; Three dimensional displays; abort-on-fail; preemptive scheduling; manufacturing test; reject-oriented analysis; stacked integrated circuit; modular test; test scheduling; System-on-chip
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2015.2409840

System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC'02 SOC Test Benchmarks show 3.5 and 20 percent reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test scheduling.