A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver

• Published in: IEEE journal of solid-state circuits Vol. 46; no. 7; pp. 1606 - 1617
• Main Authors: Murphy, D., Gu, Q. J., Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Tang, A., Wang, F., Chang, M-C F.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 60 GHz; Circuits; CMOS; CMOS integrated circuits; Consumption; Frequency synthesizers; Higher harmonics; mm-wave; Noise; Phase locked loops; Phase noise; PLL; Resonant frequency; Transceivers; Tuning; VCO; Voltage-controlled oscillators; Wideband
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2011.2143950

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting an 802.15.3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced tones from 43.2 GHz to 51.84 GHz, which is suitable for a heterodyne architecture with F LO =(4/5)×F TRX . Phase noise is measured directly at the F LO frequency and is better than -97.5 dBc/Hz@1 MHz across the entire band. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the F LO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic.