Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics

• Published in: Science (American Association for the Advancement of Science) Vol. 368; no. 6493; pp. 850 - 856
• Main Authors: Liu, Lijun, Han, Jie, Xu, Lin, Zhou, Jianshuo, Zhao, Chenyi, Ding, Sujuan, Shi, Huiwen, Xiao, Mengmeng, Ding, Li, Ma, Ze, Jin, Chuanhong, Zhang, Zhiyong, Peng, Lian-Mao
• Format: Journal Article
• Language: English
• Published: United States The American Association for the Advancement of Science 22.05.2020
• Subjects: Arrays; Carbon; Density; Dispersion; Fabrication; Field effect transistors; Gating; Integrated circuits; Ionic liquids; Metal oxides; Nanotechnology; Nanotubes; Oscillators; Performance measurement; Purity; Room temperature; Self alignment; Semiconductor devices; Silicon; Silicon transistors; Silicon wafers; Single wall carbon nanotubes; Transconductance; Transistors
• ISSN: 0036-8075; 1095-9203; 1095-9203
• DOI: 10.1126/science.aba5980

Although semiconducting carbon nanotubes (CNTs) are promising candidates to replace silicon in transistors at extremely small dimensions, their purity, density, and alignment must be improved. Liu et al. combined a multiple dispersion sorting process, which improves purity, and a dimension-limited self-alignment process to produce well-aligned CNT arrays on a 10-centimeter silicon wafer. The density is sufficiently high (100 to 200 CNTs per micrometer) that large-scale integrated circuits could be fabricated. With ionic liquid gating, the performance metrics exceeded those of conventional silicon transistors with similar dimensions. Science , this issue p. 850 Purified semiconducting carbon nanotubes were deposited on substrates at high alignment and density for transistor operation. Single-walled carbon nanotubes (CNTs) may enable the fabrication of integrated circuits smaller than 10 nanometers, but this would require scalable production of dense and electronically pure semiconducting nanotube arrays on wafers. We developed a multiple dispersion and sorting process that resulted in extremely high semiconducting purity and a dimension-limited self-alignment (DLSA) procedure for preparing well-aligned CNT arrays (within alignment of 9 degrees) with a tunable density of 100 to 200 CNTs per micrometer on a 10-centimeter silicon wafer. Top-gate field-effect transistors (FETs) fabricated on the CNT array show better performance than that of commercial silicon metal oxide–semiconductor FETs with similar gate length, in particular an on-state current of 1.3 milliamperes per micrometer and a recorded transconductance of 0.9 millisiemens per micrometer for a power supply of 1 volt, while maintaining a low room-temperature subthreshold swing of <90 millivolts per decade using an ionic-liquid gate. Batch-fabricated top-gate five-stage ring oscillators exhibited a highest maximum oscillating frequency of >8 gigahertz.