Techniques for Fast Physical Synthesis

• Published in: Proceedings of the IEEE Vol. 95; no. 3; pp. 573 - 599
• Main Authors: Alpert, Charles J., Karandikar, Shrirang K., Li, Zhuo, Nam, Gi-Joon, Quay, Stephen T., Ren, Haoxing, Sze, C. N., Villarrubia, Paul G., Yildiz, Mehmet C.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Buffers; Circuit optimization; circuit synthesis; CMOS integrated circuits; Delay; design automation; Design engineering; Electronic design automation; Floorplans; Hardware; Integrated circuit synthesis; Integrated circuits; Logic design; Placement; Productivity; Runtime; Signal design; Signal synthesis; Specifications; Synthesis; Time measurements; Timing; Wire

The traditional purpose of physical synthesis is to perform timing closure , i.e., to create a placed design that meets its timing specifications while also satisfying electrical, routability, and signal integrity constraints. In modern design flows, physical synthesis tools hardly ever achieve this...