Techniques for Fast Physical Synthesis

• Published in: Proceedings of the IEEE Vol. 95; no. 3; pp. 573 - 599
• Main Authors: Alpert, Charles J., Karandikar, Shrirang K., Li, Zhuo, Nam, Gi-Joon, Quay, Stephen T., Ren, Haoxing, Sze, C. N., Villarrubia, Paul G., Yildiz, Mehmet C.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Buffers; Circuit optimization; circuit synthesis; CMOS integrated circuits; Delay; design automation; Design engineering; Electronic design automation; Floorplans; Hardware; Integrated circuit synthesis; Integrated circuits; Logic design; Placement; Productivity; Runtime; Signal design; Signal synthesis; Specifications; Synthesis; Time measurements; Timing; Wire
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/JPROC.2006.890096

The traditional purpose of physical synthesis is to perform timing closure , i.e., to create a placed design that meets its timing specifications while also satisfying electrical, routability, and signal integrity constraints. In modern design flows, physical synthesis tools hardly ever achieve this goal in their first iteration. The design team must iterate by studying the output of the physical synthesis run, then potentially massage the input, e.g., by changing the floorplan, timing assertions, pin locations, logic structures, etc., in order to hopefully achieve a better solution for the next iteration. The complexity of physical synthesis means that systems can take days to run on designs with multimillions of placeable objects, which severely hurts design productivity. This paper discusses some newer techniques that have been deployed within IBM's physical synthesis tool called PDS that significantly improves throughput. In particular, we focus on some of the biggest contributors to runtime, placement, legalization, buffering, and electric correction, and present techniques that generate significant turnaround time improvements