A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning

• Published in: IEEE transactions on biomedical circuits and systems Vol. PP; no. 5; pp. 1 - 13
• Main Authors: Wang, Deyu, Xu, Jiawei, Li, Feng, Zhang, Lianhao, Cao, Chengwei, Stathis, Dimitrios, Lansner, Anders, Hemani, Ahmed, Zheng, Li-Rong, Zou, Zhuo
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.10.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acidity; Application specific integrated circuits; Bayesian analysis; Bayesian confidence propagation neural network (BCPNN); Biological neural networks; Computation; Computational modeling; Distance learning; Energy consumption; Engine blocks; Engines; Firing pattern; Learning; learning engine; Memristor; Memristors; Multiplication; Neural networks; Neuromorphics; online learning; Reduction; Sodium channels; spike-timing-dependent plasticity (STDP); spiking neural network (SNN); Synapses; trace dynamics; Voltage
• ISSN: 1932-4545; 1940-9990; 1940-9990
• DOI: 10.1109/TBCAS.2023.3291021

The memristor has been extensively used to facilitate the synaptic online learning of brain-inspired spiking neural networks (SNNs). However, the current memristor-based work can not support the widely used yet sophisticated trace-based learning rules, including the trace-based Spike-Timing-Dependent Plasticity (STDP) and the Bayesian Confidence Propagation Neural Network (BCPNN) learning rules. This paper proposes a learning engine to implement trace-based online learning, consisting of memristor-based blocks and analog computing blocks. The memristor is used to mimic the synaptic trace dynamics by exploiting the nonlinear physical property of the device. The analog computing blocks are used for the addition, multiplication, logarithmic and integral operations. By organizing these building blocks, a reconfigurable learning engine is architected and realized to simulate the STDP and BCPNN online learning rules, using memristors and 180 nm analog CMOS technology. The results show that the proposed learning engine can achieve energy consumption of 10.61 pJ and 51.49 pJ per synaptic update for the STDP and BCPNN learning rules, respectively, with a 147.03× and 93.61× reduction compared to the 180 nm ASIC counterparts, and also a 9.39× and 5.63× reduction compared to the 40 nm ASIC counterparts. Compared with the state-of-the-art work of Loihi and eBrainII, the learning engine can reduce the energy per synaptic update by 11.31× and 13.13× for trace-based STDP and BCPNN learning rules, respectively.