An in-place architecture for the deblocking filter in H.264/AVC

This brief presents an in-place computing design for the deblocking filter used in H.264/AVC video coding standard. The proposed in-placed computing flow reuses intermediate data as soon as data is available. Thus, the intermediate data storage is reduced to only the four 4 /spl times/ 4 blocks inst...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 53; no. 7; pp. 530 - 534
Main Authors Cheng, Chao-Chung, Chang, Tian-Sheuan, Lee, Kun-Bin
Format Journal Article
LanguageEnglish
Published New York IEEE 01.07.2006
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Automatic voltage control
Bandwidth
Circuits
CMOS
CMOS technology
Computation
Computer architecture
Counting
Data flow computing
Data storage
Deblocking filter
Design engineering
Filters
H.264/AVC
Memory
Real time
Transform coding
Very large scale integration
Video coding
VLSI architecture design
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Summary:This brief presents an in-place computing design for the deblocking filter used in H.264/AVC video coding standard. The proposed in-placed computing flow reuses intermediate data as soon as data is available. Thus, the intermediate data storage is reduced to only the four 4 /spl times/ 4 blocks instead of whole 16 /spl times/ 16 macroblock. The resulting design can achieve 100 MHz with only 13.41K gate count and support real-time deblocking operation of 2K /spl times/ 1K@30 Hz video application when clocked at 73.73 MHz by using 0.25-/spl mu/m CMOS technology.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2006.875323