A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification
This paper presents a fast analog circuit analysis algorithm, fundamental circuit-based circuit analysis, for circuits being repeatedly modified and verified in product development. The algorithm reuses previous circuit simulation result on successive changed circuit analysis to achieve simulation o...
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| Published in | IEEE transactions on computer-aided design of integrated circuits and systems Vol. 30; no. 2; pp. 308 - 313 |
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| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
New York
IEEE
01.02.2011
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subjects | |
| Online Access | Get full text |
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| Abstract | This paper presents a fast analog circuit analysis algorithm, fundamental circuit-based circuit analysis, for circuits being repeatedly modified and verified in product development. The algorithm reuses previous circuit simulation result on successive changed circuit analysis to achieve simulation operation reduction. The algorithm is implemented with SPICE simulator on linear and nonlinear circuit applications with the proposed device delta models. The experiments show that the algorithm increases the speed of the circuit simulation five to ten times over directly simulations under the same simulation accuracy. |
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| AbstractList | This paper presents a fast analog circuit analysis algorithm, fundamental circuit-based circuit analysis, for circuits being repeatedly modified and verified in product development. The algorithm reuses previous circuit simulation result on successive changed circuit analysis to achieve simulation operation reduction. The algorithm is implemented with SPICE simulator on linear and nonlinear circuit applications with the proposed device delta models. The experiments show that the algorithm increases the speed of the circuit simulation five to ten times over directly simulations under the same simulation accuracy. |
| Author | Zhou, T Y Hang Liu Tarim, Tuna Dian Zhou |
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| Cites_doi | 10.1109/ISCAS.2009.5118372 10.1109/TCAD.2003.818129 10.1109/ISCAS.2005.1464833 10.1109/ISCAS.2008.4541558 10.1023/A:1008306431147 10.1109/TCAD.2003.810742 |
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| Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Feb 2011 |
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| References | ref8 ref7 hou (ref2) 2003; 22 ref4 mccalla (ref6) 1988 ref5 hirasuna (ref9) 1999 cheney (ref10) 2007 ref1 zhou (ref3) 2010 |
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| SubjectTerms | Algorithm design and analysis Algorithms Analog circuit simulation Analog circuits behavior modeling Biological system modeling CAD circuit optimization design and verification Circuit simulation Circuits Computational modeling Computer aided design Computer simulation Deltas Design engineering Integrated circuit modeling Mathematical models Solid modeling SPICE |
| Title | A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification |
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