Hierarchical Verification of Galois Field Circuits

This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that...

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Bibliographic Details
Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 26; no. 10; pp. 1893 - 1898
Main Authors Mukhopadhyay, D., Sengar, G., Chowdhury, D.R.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.10.2007
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Architecture
Arithmetic
Boolean functions
Circuits
Composite field
Computer aided design
Computer science
Cryptography
Data structures
Design engineering
Digital signal processing
Formal verification
functional decision diagrams (DDs)
Gain
Galois fields
Hardware
hierarchical
Integrated circuits
multipliers
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Summary:This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2007.895755