An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 27; no. 3; pp. 556 - 569
• Main Authors: Chandan Karfa, Sarkar, D., Mandal, C., Kumar, P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arithmetic; Automata; Calculus; Computer science; Data visualization; Equivalence; Equivalence checking; finite state machine with data path (FSMD) models; Formal method; Formal verification; Government; High level synthesis; high-level synthesis (HLS); Mathematical models; Processor scheduling; Scheduling; Segments; Synthesis; Transformations; Very large scale integration; Formal Verification; Scheduling; FSMD models; High-level Synthesis; Equivalence Checking
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2007.913390

A formal method for checking equivalence between a given behavioral specification prior to scheduling and the one produced by the scheduler is described. Finite state machine with data path (FSMD) models have been used to represent both the behaviors. The method consists of introducing cutpoints in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints, and identifying equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. Unlike many other reported techniques, this method is strong enough to work when path segments in the original behavior are merged, a common feature of scheduling. It is also capable of verifying several arithmetic transformations and many code-motion techniques employed during scheduling. Correctness and complexity of the method have been dealt with. Experimental results for several high-level synthesis benchmarks demonstrate the effectiveness of the method.