On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

• Published in: IEEE transactions on electron devices Vol. 58; no. 8; pp. 2326 - 2336
• Main Authors: Mazurier, J., Weber, O., Andrieu, F., Toffoli, A., Rozeau, O., Poiroux, T., Allain, F., Perreau, P., Fenouillet-Beranger, C., Thomas, O., Belleville, M., Faynot, O.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Calibration; Circuits; Computer simulation; Correlation; Depletion; Fluctuation; Fully depleted silicon-on-insulator (FDSOI) technology; Logic gates; MOSFETs; Performance evaluation; Random access memory; six-transistor static random-access memory (6T-SRAM) cells; static noise margin (SNM); Static random access memory; Threshold voltage; threshold voltage variability; Tin
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2157162

In this paper, an in-depth variability analysis, i.e., from the threshold voltage V T of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local V T variability σ(V) T lower than A(V) T = 1.4 mV · μm is demonstrated. We investigated how this good V T variability is reported on the SNM fluctuations σ SNM at the SRAM circuit level. It is found experimentally that σ SNM is correlated directly to the σ(V) T of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The V T variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V) T in drive nMOSFETs is the key parameter to control for minimizing σ SNM .