Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

• Published in: IEEE transactions on electron devices Vol. 57; no. 7; pp. 1527 - 1538
• Main Authors: Ibe, Eishi, Taniguchi, Hitoshi, Yahagi, Yasuo, Shimbo, Ken-ichi, Toba, Tadanobu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Bit multiplicity; cosmic ray impact simulator (CORIMS); Devices; Field tests; Ions; Layout; Monte Carlo methods; multi-cell upset (MCU); multi-node upset (MNU); Neutrons; Nuclear reactions; Numerical models; Protons; Random access memory; scaling; Silicon; Simulation; single event upset (SEU); Soft errors; Spreads; static random access memories (SRAMs)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2010.2047907

Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.