CRRES microelectronic test chip orbital data. II

• Published in: IEEE transactions on nuclear science Vol. 39; no. 6; pp. 1840 - 1845
• Main Authors: Soli, G.A., Blaes, B.R., Buehler, M.G., Ray, K., Lin, Y.-S.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Legacy CDMS IEEE 01.12.1992; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Degradation; Design. Technologies. Operation analysis. Testing; Electronics; Electronics And Electrical Engineering; Exact sciences and technology; Extraterrestrial measurements; Integrated circuits; Laboratories; Microelectronics; MOSFET circuits; Propulsion; Radiation effects; Satellites; Semiconductor device measurement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testing
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/23.211375

Data from a MOSFET matrix on two JPL (CIT Jet Propulsion Laboratory) CRRES (Combined Release and Radiation Effects Satellite) chips, each behind different amounts of shielding, are presented. Space damage factors are nearly identical to ground test values for pMOSFETs. The results from neighboring rows of MOSFETs show similar radiation degradation. The SRD (Space Radiation Dosimeter) is used to measure the total dose accumulated by the JPL chips. A parameter extraction algorithm that does not underestimate threshold voltage shifts is used. Temperature effects are removed from the MOSFET data.< >