A Novel Capacitorless DRAM Cell Using Superlattice Bandgap-Engineered (SBE) Structure With 30-nm Channel Length

• Published in: IEEE transactions on nanotechnology Vol. 10; no. 5; pp. 1023 - 1030
• Main Authors: LEE, Sunyeong, JA SUN SHIN, JANG, Jaeman, BAE, Hagyoul, YUN, Daeyoun, JIEUN LEE, DAE HWAN KIM, DONG MYONG KIM
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 2-D TCAD; Applied sciences; capacitorless dynamic random access memory (DRAM); Channels; Compound structure devices; Cross-disciplinary physics: materials science; rheology; Density; Design. Technologies. Operation analysis. Testing; Dynamic random access memory; Electronics; Exact sciences and technology; Gates; Germanium; Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; Materials science; Nanoscale materials and structures: fabrication and characterization; Photonic band gap; Physics; Quantum wells; Random access memory; retention; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; sensing margin; Sensors; Silicon; Silicon dioxide; silicon dioxide (SiO _2 ) physical barrier; Silicon germanides; Silicon germanium; superlattice; Superlattices; physical barrier; Circuit design; High density; Random access memory; Ge-Si alloys; IV-VI compound; Implementation; 2-D TCAD; Non volatile memory; Recording density; silicon dioxide (SiO; sensing margin; Computer aided design; retention; Binary alloy; Dynamic random access memory; Capacitor less circuit; Semiconductor alloys; Quantum well; capacitorless dynamic random access memory (DRAM); Retention factor; Common source configuration; Silicon oxides; Integrated circuit; Superlattice
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2010.2098885

We propose a novel SiGe superlattice bandgap-engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with 30-nm channel length as a next-generation DRAM cell with high storage density and long retention time for practical implementation by 2-D technology computer-aided design simulation. The SBE capacitorless DRAM cell uses a common source structure and different metal layers for the top gate word line (WL) from the bottom gate WL to realize a 6F 2 feature size. Thanks to the Si 0.8 Ge 0.2 superlattice quantum well and silicon dioxide (SiO 2 ) physical barrier, we obtained 213 μA/μm for the sensing margin and about 10 ms for the retention time.