Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 54; no. 2; pp. 146 - 150
• Main Authors: Radulov, G.I., Heydenreich, M., van der Hofstad, R.W., Hegt, J.A., van Roermund, A.H.M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Architecture; Bridges; Brownian Bridge (BB); Chip formation; Chips; Circuits; Deviation; Digital-analog conversion; digital-analog converter (DAC); integrated nonlinearity (INL); Linearity; Mathematical analysis; mismatch; Monte Carlo methods; Probability density function; Probability density functions; Production; Random variables; Silicon; static linearity; Statistical analysis; Studies; Terrorism; Thermometers
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2006.886900

This brief analytically investigates the digital-analog converter (DAC) integrated nonlinearity (INL) with respect to the accuracy of the DAC unit elements. The main novelty of the presented approach is in the application of the Brownian Bridge (BB) process to precisely describe the INL. This method analyzes the thermometer and binary DAC architectures and is the first to prove that their statistical INL properties are different. The INL of the thermometer DAC is represented as a one-dimensional BB process. For the binary case, the INL is represented as combinations of random variables, the increments of which coincide with a BB process. For both architectures, this brief derives formulas for the INL main statistical properties, e.g., probability density function, mean, deviation, and chip yield. These properties are compared with previous analytical attempts and conclusions are drawn. The results of this brief fill a gap in the general understanding of the most quoted DAC specification- the INL. In particular, for a high-volume chip production, the derived formulas will help engineers to choose the DAC architecture and the allowed mismatch of the DAC unit elements