A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 27; no. 9; pp. 1535 - 1544
• Main Authors: Fujiwara, H., Iwata, H., Yoneda, T., Chia Yee Ooi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acyclic testability; at-speed testing; Circuit faults; Circuit testing; Circuits; Cities and towns; Combinational circuits; Costs; Design engineering; Design for testability; Design methodology; Faults; Flip-flops; Hardware; Mathematical analysis; Mathematical models; register transfer level (RTL); Sequential analysis; Sequential circuits; Studies; test generation complexity; Test pattern generators; Testability
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2008.927757

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.