A 5.2 GHz low-voltage low-noise amplifier with 0.35 μm CMOS technology
A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35 µm CMOS high-frequency model to design a fully integrated 1 V, 5.2 GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source wit...
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Published in | International journal of electronics Vol. 91; no. 9; pp. 551 - 561 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
London
Taylor & Francis Group
01.09.2004
Taylor & Francis |
Subjects | |
Online Access | Get full text |
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Summary: | A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35 µm CMOS high-frequency model to design a fully integrated 1 V, 5.2 GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50 Ω. The simulation results show that the amplifier provides a gain of 9.48 dB, a noise figure of 4.08 dB, and draws 13.4 mW from a 1 V supply. The S11 and S22 are both lower than −15 dB. |
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ISSN: | 0020-7217 1362-3060 |
DOI: | 10.1080/00207210412331319083 |