Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies

• Published in: IEEE transactions on electron devices Vol. 58; no. 8; pp. 2347 - 2353
• Main Authors: Magnone, P., Crupi, F., Wils, N., Jain, R., Tuinhout, H., Andricciola, P., Giusi, G., Fiegna, C.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Carriers; Charge; CMOS integrated circuits; CMOS technology; Devices; Electric charge; Evolution; Hot carrier (HC); Logic gates; Mathematical models; metal-oxide-semiconductor field-effect transistor (MOSFET); mismatch; MOSFET circuits; Semiconductor device modeling; Statistical analysis; Stress; Stresses; Studies; subthreshold slope; threshold voltage; Transistors; variability
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2156414

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.