A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider

• Published in: IEEE journal of solid-state circuits Vol. 43; no. 2; pp. 477 - 485
• Main Author: Razavi, B.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.02.2008; Institute of Electrical and Electronics Engineers
• Subjects: 60-GHz transceivers; Applied sciences; Circuit properties; Circuits; CMOS; CMOS technology; Current-domain circuits; Design. Technologies. Operation analysis. Testing; Digital circuits; Dividers; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Floors; Frequency conversion; Gain; Inductors; Integrated circuit interconnections; Integrated circuits; Integrated circuits by function (including memories and processors); Integrated optics. Optical fibers and wave guides; Miller divider; Millimeter wave communication; Millimeter wave technology; mm-wave communication; nested inductors; Nesting; Noise figure; Noise levels; Optical and optoelectronic circuits; Oscillators; polyphase filter; Receivers; RF receivers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transceivers; Noise figure; polyphase filter; mm-wave communication; Mixer; Microwave; Inductor; Transceiver; Millimetric wave; Wide band; Oscillator; Complementary MOS technology; Optical receiver; CMOS integrated circuits; Arithmetic circuit; Miller divider; Heterodyne receivers; nested inductors; Mismatching; Interconnection; Current-domain circuits; Integrated circuit; 60-GHz transceivers; RF receivers; Radio receivers; Circuit noise; High frequency; Divider; Gain
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2007.914300

A heterodyne receiver performs frequency down-conversion in two steps to relax oscillator and divider speed requirements. The receiver incorporates new concepts such as a current-domain quadrature separation method, a broadband Miller divider based on a passive mixer, and an inductor nesting technique that significantly reduces the length of high-frequency interconnects. Fabricated in 90-nm CMOS technology, the circuit achieves a noise figure of 6.9 to 8.3 dB from 49 GHz to 53 GHz with a gain of 26 to 31.5 dB and I/Q mismatch of 1.6 dB/6.5deg.