Copper-filled macroporous Si and cavity underneath for microchannel heat sink technology

• Published in: Physica status solidi. A, Applications and materials science Vol. 205; no. 11; pp. 2513 - 2517
• Main Authors: Zacharatos, F., Nassiopoulou, A. G.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Berlin WILEY-VCH Verlag 01.11.2008; WILEY‐VCH Verlag; Wiley-VCH
• Subjects: 81.05.Rm; 81.15.Pq; 82.45.Vp; 85.40.−e; 85.85.+j; Applied sciences; Design. Technologies. Operation analysis. Testing; Electrical engineering. Electrical power engineering; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Integrated circuits; Power electronics, power supplies; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Nucleation; Thermal management (packaging); Integration density; High density; Thermal behavior; Power electronics; Two dimensional model; Porous material; Microcavity; Composite material; Pore size; Electrochemical properties; Power consumption; Cavity; Anodizing; Cooling system; Heat sink; Wafer; Heat transfer
• ISSN: 1862-6300; 1862-6319
• DOI: 10.1002/pssa.200780161

Thermal management in ICs becomes essential as integration density and total power consumption increase. The use of microchannels in high power density electronics cooling is a well‐known technique for heat transfer. In this work we developed Cu‐filled macroporous Si channels with a Cu‐filled cavity underneath, which may be used as heat sinks in high power density electronics cooling. Macroporous Si is formed by electrochemical dissolution of bulk Si, while pore filling with copper is achieved by electro‐deposition. Using appropriate design, the resulting composite material may be fabricated on selected areas on the silicon substrate for use as heat sink on Si. The surface area is defined by patterning. The macroporous Si structure is composed of either randomly distributed pores or pores arranged in two‐dimensional (2‐D) arrays, fabricated by pre‐patterning the Si surface before anodization so as to form pore initiation pits. The pore size in this work was 5μm, while the porous layer and the cavity underneath had both a thickness of 40 μm. Copper deposition proceeds first by filling the micro‐cavity underneath the porous layer. This is achieved by linearly increasing the applied potential during electro‐deposition. After full Cu‐filling of the cavity, pore filling starts from the bottom of each pore and proceeds laterally, while no nucleation takes place on pore wall. In this way, homogeneous copper wires within pores may be fabricated. The Cu/Si composite material is appropriate for forming channels with improved heat transfer within the Si wafer. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)