OpenSPARC Processor Evaluation Using Virtex-5 FPGA and High Performance Embedded Computing (HPEC) Benchmark Suite

• Published in: International journal of embedded and real-time communication systems Vol. 5; no. 1; pp. 61 - 74
• Main Authors: Mhaidat, Khaldoon Moosa, Baset, Ahmad, Al-Khaleel, Osama
• Format: Journal Article
• Language: English
• Published: Hershey IGI Global 01.01.2014
• Subjects: Benchmarks; Computation; Embedded systems; Field programmable gate arrays; Microprocessors; Performance evaluation; Prototyping; Synthesis
• ISSN: 1947-3176; 1947-3184
• DOI: 10.4018/ijertcs.2014010104

OpenSPARC is the only 64-bit Chip Multi-Threaded (CMT) processor that has ever been made open-source and non-proprietary. In this paper, the authors present an FPGA-based embedded system and methodology for prototyping and validating the OpenSPARC processor. They also present synthesis and performance evaluation results for OpenSPARC on a Virtex-5 FPGA platform. Light version of OpenSolaris was successfully booted on the platform, and the High Performance Embedded Computing (HPEC) benchmark suite was used to evaluate the performance. Xilinx ISE suite was used for synthesis, implementation, and chip programming. The down-scaled FPGA implementation of the processor runs at 81.3 MHz. The whole processor would require about 176453 Virtex-5 logic slices. To the best of their knowledge, they are the first researchers to report detailed FPGA synthesis results for OpenSPARC and evaluate its performance on FPGA using the HPEC benchmarks. Other researchers may find these results useful when comparing with other processors or studying the impact of a certain design change or addition on performance and cost.