A novel dual-feed low-dropout regulator

A novel dual-feed （DF） low-dropout （LDO） is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of t...

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Bibliographic Details
Published inJournal of semiconductors Vol. 36; no. 6; pp. 110 - 114
Main Author 段志奎 胡建国 丁一 路崇 丁颜玉 王德明 谭洪舟
Format Journal Article
LanguageEnglish
Published Chinese Institute of Electronics 01.06.2015
Subjects
CMOS工艺
Control systems
Control theory
damping ratio
DF-LDO
dual-feed
Electric potential
fast transient response
Feedforward
natural frequency
Semiconductors
Settling
Voltage
Workload
低压降稳压器
双馈
反馈环路
控制回路
瞬态性能
自然频率
输出电压
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Summary:A novel dual-feed （DF） low-dropout （LDO） is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 #F decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.
Bibliography:11-5781/TN
dual-feed; fast transient response; DF-LDO; damping ratio; natural frequency
A novel dual-feed （DF） low-dropout （LDO） is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 #F decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.
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SourceType-Scholarly Journals-1
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ISSN:1674-4926
DOI:10.1088/1674-4926/36/6/065003