A high-speed 7 bit A/D converter

A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals u...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 14; no. 6; pp. 938 - 943
Main Authors Van De Plassche, R.J., Van Der Grift, R.E.J.
Format Journal Article
LanguageEnglish
Published IEEE 01.12.1979
Subjects
Circuits
Complexity theory
Cost function
Delay
Density estimation robust algorithm
Diodes
Frequency
Large scale integration
Resistors
Signal sampling
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Summary:A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals up to 5 MHz can be digitally sampled with sampling frequencies up to 50 MHz. A double layer metallization process is used to reduce the die size to 2.4/spl times/2.5 mm.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1979.1051301