A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 17; no. 10; pp. 1461 - 1469
• Main Authors: KIM, Moo-Young, SHIN, Dongsuk, CHAE, Hyunsoo, KIM, Chulwoo
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clock generator; Clock generators; clock-on-demand; Clocks; Clocks & watches; CMOS; Delay lines; Design. Technologies. Operation analysis. Testing; Detectors; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frequency; General equipment and techniques; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuits; IP (Internet Protocol); Jitter; lock time; Microprocessors; Multiphase; Oscillators, resonators, synthetizers; Phase detection; Phase locked loops; Physics; PLL; Portability; portable; Power generation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing; Signal generators; Very large scale integration; clock-on-demand; Clock generator; High resolution; Measurement sensor; Jitter; portable; Clock; Phase locked loop; PLL; Electronic generator; Complementary MOS technology; Open loop; lock time; Signal generators; Portable equipment; Distance measurement; Phase delay; Delay time; Delay line; Execution time
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2008.2004591

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.