Code Decompression Unit Design for VLIW Embedded Processors
Code size "bloating" in embedded very long instruction word (VLIW) processors is a major concern for embedded systems since memory is one of the most restricted resources. In this paper, we describe a code compression algorithm based on arithmetic coding, discuss how to design decompressio...
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Published in | IEEE transactions on very large scale integration (VLSI) systems Vol. 15; no. 8; pp. 975 - 980 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
Piscataway, NJ
IEEE
01.08.2007
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
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Abstract | Code size "bloating" in embedded very long instruction word (VLIW) processors is a major concern for embedded systems since memory is one of the most restricted resources. In this paper, we describe a code compression algorithm based on arithmetic coding, discuss how to design decompression architecture, and illustrate the tradeoffs between compression ratio and decompression overhead, by using different probability models. Experimental results for a VLIW embedded processor TMS320C6x show that compression ratios between 67% and 80% can be achieved, depending on the probability models used. A precache decompression unit design is implemented in TSMC 0.25 mum and a test chip is fabricated. |
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AbstractList | Code size "bloating" in embedded very long instruction word (VLIW) processors is a major concern for embedded systems since memory is one of the most restricted resources. In this paper, we describe a code compression algorithm based on arithmetic coding, discuss how to design decompression architecture, and illustrate the tradeoffs between compression ratio and decompression overhead, by using different probability models. Experimental results for a VLIW embedded processor TMS320C6x show that compression ratios between 67% and 80% can be achieved, depending on the probability models used. A precache decompression unit design is implemented in TSMC 0.25 mum and a test chip is fabricated. |
Author | Yuan Xie Lekatsas, H. Wolf, W. |
Author_xml | – sequence: 1 surname: Yuan Xie fullname: Yuan Xie organization: Pennsylvania State Univ., University Park – sequence: 2 givenname: W. surname: Wolf fullname: Wolf, W. – sequence: 3 givenname: H. surname: Lekatsas fullname: Lekatsas, H. |
BackLink | http://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18947846$$DView record in Pascal Francis |
BookMark | eNp9kEFLwzAUx4MouE0_gHgpguKl8700SVs8yZw6KCi4zWPI0kQ6tmYm28Fvb-aGggdzSELye__k_brksHWtIeQMoY8I5c14Wr2O-hQg75dx4vyAdJDzPC3jOIx7EFlaUIRj0g1hDoCMldAhtwNXm-TeaLdceRNC49pk0jbreBSa9zaxzifTavSWDJczU9emTl680xF0PpyQI6sWwZzu1x6ZPAzHg6e0en4cDe6qVGeFWKeWCmOMQAGWY14roSjWohaQZTanDGYWOM7UjCMFFLk1mlNNC8rL-ENuRdYjV7vclXcfGxPWctkEbRYL1Rq3CTJjnDOBNILX_4IxHTMoWXy5Ry7-oHO38W1sQ5ZIKWdQbCHcQdq7ELyxcuWbpfKfEkFutctv7XKrXe60x5rLfbAKWi2sV61uwm9hUbK8YNumzndcE-X8XDOai7wosi_dKooO |
CODEN | IEVSE9 |
CitedBy_id | crossref_primary_10_1007_s12652_020_02497_8 crossref_primary_10_1016_j_sysarc_2013_11_001 |
Cites_doi | 10.1016/0020-0190(96)00090-7 10.1109/TVLSI.2006.876105 10.1109/TIT.1977.1055714 10.1109/MICRO.1992.697002 10.1147/rd.426.0807 10.1109/43.811316 |
ContentType | Journal Article |
Copyright | 2007 INIST-CNRS Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2007 |
Copyright_xml | – notice: 2007 INIST-CNRS – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2007 |
DBID | 97E RIA RIE IQODW AAYXX CITATION 7SP 8FD L7M F28 FR3 |
DOI | 10.1109/TVLSI.2007.900755 |
DatabaseName | IEEE All-Society Periodicals Package (ASPP) 2005-present IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) Pascal-Francis CrossRef Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace ANTE: Abstracts in New Technology & Engineering Engineering Research Database |
DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts Engineering Research Database ANTE: Abstracts in New Technology & Engineering |
DatabaseTitleList | Engineering Research Database Engineering Research Database |
Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Engineering Applied Sciences |
EISSN | 1557-9999 |
EndPage | 980 |
ExternalDocumentID | 2544982091 10_1109_TVLSI_2007_900755 18947846 4276788 |
Genre | orig-research |
GroupedDBID | -~X .DC 0R~ 29I 3EH 4.4 5GY 5VS 6IK 97E AAJGR AASAJ AAYOK ABFSI ABQJQ ABVLG ACGFS ACIWK AENEX AETIX AI. AIBXA AKJIK ALLEH ALMA_UNASSIGNED_HOLDINGS ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 E.L EBS EJD HZ~ H~9 ICLAB IEDLZ IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P RIA RIC RIE RIG RNS TN5 VH1 XFK IQODW AAYXX CITATION 7SP 8FD L7M F28 FR3 |
ID | FETCH-LOGICAL-c386t-f26eee6160f517da6a21d6d6033f7240bf051bab5120167fec52c282594905f63 |
IEDL.DBID | RIE |
ISSN | 1063-8210 |
IngestDate | Fri Aug 16 02:16:15 EDT 2024 Fri Aug 16 21:59:24 EDT 2024 Fri Sep 13 07:02:52 EDT 2024 Fri Aug 23 01:11:07 EDT 2024 Sun Oct 22 16:07:49 EDT 2023 Wed Jun 26 19:26:47 EDT 2024 |
IsPeerReviewed | true |
IsScholarly | true |
Issue | 8 |
Keywords | Code compression Boarded computer Very long instruction word Embedded systems Processor Integrated circuit testing Coding Integrated circuit embedded system Algorithm |
Language | English |
License | CC BY 4.0 |
LinkModel | DirectLink |
MergedId | FETCHMERGED-LOGICAL-c386t-f26eee6160f517da6a21d6d6033f7240bf051bab5120167fec52c282594905f63 |
Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 ObjectType-Article-2 ObjectType-Feature-1 |
PQID | 912254083 |
PQPubID | 23500 |
PageCount | 6 |
ParticipantIDs | pascalfrancis_primary_18947846 ieee_primary_4276788 proquest_miscellaneous_34554612 proquest_miscellaneous_1671309403 proquest_journals_912254083 crossref_primary_10_1109_TVLSI_2007_900755 |
PublicationCentury | 2000 |
PublicationDate | 2007-08-01 |
PublicationDateYYYYMMDD | 2007-08-01 |
PublicationDate_xml | – month: 08 year: 2007 text: 2007-08-01 day: 01 |
PublicationDecade | 2000 |
PublicationPlace | Piscataway, NJ |
PublicationPlace_xml | – name: Piscataway, NJ – name: New York |
PublicationTitle | IEEE transactions on very large scale integration (VLSI) systems |
PublicationTitleAbbrev | TVLSI |
PublicationYear | 2007 |
Publisher | IEEE Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher_xml | – name: IEEE – name: Institute of Electrical and Electronics Engineers – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
References | ref8 ref7 (ref3) 1997 ref6 ref5 fisher (ref4) 2005 ref2 ref1 |
References_xml | – ident: ref7 doi: 10.1016/0020-0190(96)00090-7 – year: 1997 ident: ref3 publication-title: TMS320C62xx CPU and instruction set Reference guide – ident: ref6 doi: 10.1109/TVLSI.2006.876105 – ident: ref8 doi: 10.1109/TIT.1977.1055714 – ident: ref1 doi: 10.1109/MICRO.1992.697002 – ident: ref2 doi: 10.1147/rd.426.0807 – ident: ref5 doi: 10.1109/43.811316 – year: 2005 ident: ref4 publication-title: Embedded Computing A VLIW Approach to Architecture Compiler and Tools contributor: fullname: fisher |
SSID | ssj0014490 |
Score | 1.8594016 |
Snippet | Code size "bloating" in embedded very long instruction word (VLIW) processors is a major concern for embedded systems since memory is one of the most... |
SourceID | proquest crossref pascalfrancis ieee |
SourceType | Aggregation Database Index Database Publisher |
StartPage | 975 |
SubjectTerms | Applied sciences Arithmetic coding Automatic testing Built-in self-test Chip formation Circuit testing Code compression Compressing Compression ratio Design engineering Design. Technologies. Operation analysis. Testing Electronics Embedded computer systems Embedded system Ethernet networks Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Logic testing Processors Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sequential analysis System testing Very large scale integration VLIW |
Title | Code Decompression Unit Design for VLIW Embedded Processors |
URI | https://ieeexplore.ieee.org/document/4276788 https://www.proquest.com/docview/912254083/abstract/ https://search.proquest.com/docview/1671309403 https://search.proquest.com/docview/34554612 |
Volume | 15 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LT9wwEB4Bp3IolIcaoEsq9YTIYjuOY6snRFlBBVx43iLbsS-IBLG7F3494zi7LY9KvUWJFdkz9sxnzzdjgB-KE02lpJklhc04bq8zrYnJmMh1kSvDCxpyh88vxMk1_31X3C3A_jwXxjnXkc_cMDx2sfy6tdNwVHbAWYm2VS7CoiQs5mrNIwacq1h5QOSZxH1MH8GkRB1c3ZxdnsZqhSq4yOKVD-ouVQmUSD1Gqfh4ncU7y9y5m9EKnM86Glkm98PpxAzt85sajv87klX43OPO9DBOlC-w4Jo1WP6rGuE6_Dxqa5f-coFlHtmxTRogKb4KLI8U4W16c3Z6mx4_GIf2qk77LIP2abwB16Pjq6OTrL9bIbO5FJPMM4GdElQQX9Cy1kIzWotakDz3JXp543G1Gm0QD4REBe9swWzIc1Uo58KLfBOWmrZxXyGljllfawSWRnHpmPShbDzRyttS1kwmsDeTdvUYS2hU3daDqKpTTbgKs6yiahJYD9KaN-wFlcDglX7-_EgqXiKGSmB7prCqX4XjSlG0VhxBZgLf519x-YSYiG5cOx1XODb04jhjsc3uP9rkPFD5KNv6uG_b8Cke-AZW4A4sTZ6m7hsilYkZdFP0BbzV4xo |
link.rule.ids | 315,786,790,802,27957,27958,55109 |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3dT9swED8x9sD2MDYYWlZWMoknRNrYcRxbe0IM1I6WFwrjLbId-2VaMtH2ZX_9znFaxsekvUXJKbLv7Luz73d3AIeSpYoIQRKT5iZheLxOlEp1Qnmm8kxqlhOfOzy95KNr9u02v92A43UujLW2BZ_ZgX9sY_lVY5b-qmzIaIG6VbyAl2jnUxmytdYxA8ZkqD3As0TgSaaLYSLhcHYzuRqHeoXSG8n8gRVq26p4UKSaI19caGjxRDe3Bud8G6aroQacyY_BcqEH5vejKo7_O5e38KbzPOOTsFTewYatd-D1X_UId-HLaVPZ-Kv1OPOAj61j75TiK4_ziNHBjW8m4-_x2U9tUWNVcZdn0NzN38P1-dnsdJR03RUSkwm-SBzlOChOeOpyUlSKK0oqXvE0y1yBdl473K9aafQIfKqCsyanxme6SuRz7ni2B5t1U9sPEBNLjasUupZaMmGpcL5wfKqkM4WoqIjgaMXt8lcoolG2h49Ulq1ofDPMogyiiWDXc2tN2DEqgv4D-dz_SEhWoBcVQW8lsLLbh_NSEtRXDN3MCD6vv-IG8lERVdtmOS9xbmjHcc0izcE_aDLmwXyEfnx-bAewNZpNJ-VkfHnRg1fh-tdjBPdhc3G3tJ_Qb1nofrtc_wDgVuZw |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Code+Decompression+Unit+Design+for+VLIW+Embedded+Processors&rft.jtitle=IEEE+transactions+on+very+large+scale+integration+%28VLSI%29+systems&rft.au=Yuan+Xie&rft.au=Wolf%2C+W.&rft.au=Lekatsas%2C+H.&rft.date=2007-08-01&rft.pub=IEEE&rft.issn=1063-8210&rft.eissn=1557-9999&rft.volume=15&rft.issue=8&rft.spage=975&rft.epage=980&rft_id=info:doi/10.1109%2FTVLSI.2007.900755&rft.externalDocID=4276788 |
thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1063-8210&client=summon |
thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1063-8210&client=summon |
thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1063-8210&client=summon |