Code Decompression Unit Design for VLIW Embedded Processors

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 15; no. 8; pp. 975 - 980
• Main Authors: Yuan Xie, Wolf, W., Lekatsas, H.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.08.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Arithmetic coding; Automatic testing; Built-in self-test; Chip formation; Circuit testing; Code compression; Compressing; Compression ratio; Design engineering; Design. Technologies. Operation analysis. Testing; Electronics; Embedded computer systems; Embedded system; Ethernet networks; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Logic testing; Processors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sequential analysis; System testing; Very large scale integration; VLIW; Code compression; Boarded computer; Very long instruction word; Embedded systems; Processor; Integrated circuit testing; Coding; Integrated circuit; embedded system; Algorithm
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2007.900755

Code size "bloating" in embedded very long instruction word (VLIW) processors is a major concern for embedded systems since memory is one of the most restricted resources. In this paper, we describe a code compression algorithm based on arithmetic coding, discuss how to design decompression architecture, and illustrate the tradeoffs between compression ratio and decompression overhead, by using different probability models. Experimental results for a VLIW embedded processor TMS320C6x show that compression ratios between 67% and 80% can be achieved, depending on the probability models used. A precache decompression unit design is implemented in TSMC 0.25 mum and a test chip is fabricated.