A Compact High-Efficiency CMOS Power Amplifier With Built-in Linearizer

In this letter, a compact high-efficiency CMOS power amplifier (PA) with built-in linearizer that works at 2.4 GHz using TSMC 0.18 mum technology for digital wireless communications applications is presented. The cascode configuration is utilized to overcome the low break-down voltage problem and th...

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Bibliographic Details
Published inIEEE microwave and wireless components letters Vol. 19; no. 9; pp. 587 - 589
Main Authors HUANG, Chien-Chang, LIN, Wu-Chieh
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.09.2009
Institute of Electrical and Electronics Engineers
Subjects
Amplifiers
Applied sciences
Circuit properties
Circuits
CMOS
Design. Technologies. Operation analysis. Testing
Distortion
Electric potential
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Heterojunction bipolar transistors
High power amplifiers
Integrated circuits
Linearity
linearization
Microwaves
Noise levels
Nonlinear distortion
OFDM
power amplifier
Power amplifiers
Power generation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transceivers
Voltage
Wireless communication
Performance evaluation
Output power
Third order
Wireless telecommunication
Compact design
Power electronics
Cascode connection
Low voltage
CMOS
nonlinear distortion
High power
Intercept point
Complementary MOS technology
Hot carrier
Digital communication
Power amplifier
Signal distortion
Linearization
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Summary:In this letter, a compact high-efficiency CMOS power amplifier (PA) with built-in linearizer that works at 2.4 GHz using TSMC 0.18 mum technology for digital wireless communications applications is presented. The cascode configuration is utilized to overcome the low break-down voltage problem and the hot-carrier effects for high power operations of CMOS devices. The linearizer design reduces the AM-AM quantities to extend the P 1 dB point while the AM-PM distortions are improved as well. The final designed PA exhibits P 1 dB of 20.6 dBm and 24.6% power-added-efficiency (PAE) with 35 dBm output-intercept-point in the third order (OIP3). The saturated output power is 22 dBm with 30% in PAE, while the chip size is less than 1 mm 2 .
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1531-1309
1558-1764
DOI:10.1109/LMWC.2009.2027093