Failure Analysis of Si Nanowire Field-Effect Transistors Subject to Electrostatic Discharge Stresses

• Published in: IEEE electron device letters Vol. 31; no. 9; pp. 915 - 917
• Main Authors: Wen Liu, Liou, Juin J, Jiang, Y, Singh, Navab, Lo, G Q, Chung, J, Jeong, Y H
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Current measurement; Degradation; Devices; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Electrostatic analysis; Electrostatic discharge; electrostatic discharge (ESD); Electrostatic discharges; Exact sciences and technology; Failure analysis; FETs; gate oxide breakdown; Microscopy; Nanocomposites; Nanomaterials; Nanoscale devices; Nanostructure; nanowire field-effect transistor (NW FET); Nanowires; Pulse measurements; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Stress; Stresses; Testing, measurement, noise and reliability; Transistors; Voltage current curve; nanowire field-effect transistor (NW FET); Oxide layer; Electrostatic discharge; Transistor gate; Failures; Field effect transistor; Degradation; Transmission line; Nanowire device; Gate oxide; Failure analysis; Testing equipment; Nanowires; Reliability; electrostatic discharge (ESD); Electrical characteristic; Damaging; gate oxide breakdown
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2010.2052911

The failure mechanisms of silicon nanowire field-effect transistors subject to electrostatic discharge (ESD) stresses are investigated using electrical characterization and microscopy analysis. Current-voltage measurements are carried out before and after the devices are stressed with ESD equivalent pulses generated from the transmission line pulsing (TLP) tester. Depending on the TLP stress level, either a soft or a hard failure can take place in the nanowire devices due to the nondestructive damage or destructive fusing of nanowires and the surrounding gate oxide.