CORDIC-based architecture with channel state information for OFDM baseband receiver

• Published in: IEEE transactions on consumer electronics Vol. 51; no. 2; pp. 403 - 412
• Main Authors: Peng, Chia-Sheng, Chuang, Yuan-Shin, Wen, Kuei-Ann
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2005; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Architecture; AWGN; Baseband; Channel state information; Channels; Computer architecture; Computer simulation; Digital computers; Error analysis; Field programmable gate arrays; Frequency estimation; Frequency synchronization; Mathematical models; OFDM; Offsets; Orthogonal Frequency Division Multiplexing; Receivers; Sampling methods; Semiconductor device modeling; Synchronism
• ISSN: 0098-3063; 1558-4127
• DOI: 10.1109/TCE.2005.1467979

An efficient architecture for OFDM baseband receiver based on coordinate rotation digital computer (CORDIC) algorithm is proposed with channel state information (CSI). Two dual-mode CORDIC modules are designed for synchronization and equalization. A modified demapping method using CSI helps to provide sub-channel status, and therefore decreases the packet error rates especially for some sub-channels with extremely low SNR. A combined algorithm suitable for CORDIC is proposed for not only the estimation and compensation of channels but synchronization for carrier frequency offset and sampling clock offset. Allocation, timing analysis and complexity for all functional blocks in the receiver are proposed, including front-end processing, FFT, inner receiver, and outer receiver. Complete tests for packet error rate are simulated under an integrated platform considering of RF front-end non-ideal parameters, filters, quantization, and channel models. Simulation results of practical circuits on AWGN and channel models are presented and prove the improvement of the receiver. The design occupies about 424 k equivalent gate count and 7.3 mm/sup 2/ core size in 0.18-/spl mu/m CMOS.