A 16-Mb Toggle MRAM With Burst Modes

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 11; pp. 2378 - 2385
• Main Authors: Sugibayashi, T., Sakimura, N., Honda, T., Nagahara, K., Tsuji, K., Numata, H., Miura, S., Shimura, K., Kato, Y., Saito, S., Fukumoto, Y., Honjo, H., Suzuki, T., Suemitsu, K., Mukai, T., Mori, K., Nebashi, R., Fukami, S., Ohshima, N., Hada, H., Ishiwata, N., Kasai, N., Tahara, S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Burst mode; Bursting; Circuits; Clocks; CMOS; CMOS process; Disturbances; Equivalent circuits; Frequency; Magnetic fields; magnetic random access memory (MRAM); Magnetic tunneling; Magnetization; Magnetoresistive random access memory; pseudo-SRAM; Random access memory; Switches; toggle cell; Writing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2007.906195

This paper describes a recently developed 16-Mb toggle magnetic random access memory (MRAM). It has 100-MHz burst modes that are compatible with a pseudo-SRAM even though the toggle cell requires reading and comparing sequences in write modes. To accelerate operating clock frequency, we propose a distributed-driver wide-swing current-mirror scheme, an interleaved and pipelined memory-array group activation scheme, and a noise-insulation switch scheme. These circuit schemes compensate the toggle cell timing overhead in write modes and maintain write-current precision that is essential for the wide operational margin of MRAMs. Because toggle cells are very resistant to write disturbance errors, we designed the 16-Mb MRAM to include a toggle MRAM cell. The MRAM was fabricated with 0.13-mum CMOS and 0.24-mum MRAM processes with five metal layers.