Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

• Published in: Microelectronics and reliability Vol. 120; pp. 1 - 8
• Main Authors: Marques, Ivo, Rodrigues, Cristiano, Tavares, Adriano, Pinto, Sandro, Gomes, Tiago
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.05.2021; Elsevier
• Subjects: Arm; Design diversity; Dual-core lockstep; Fault tolerance; Field-programmable gate array; RISC-V; Science & Technology; Design diversity; Field-programmable gate array; RISC-V; Fault tolerance; Dual-core lockstep; Arm

This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two...