Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two...

Full description

Saved in:
Bibliographic Details
Published inMicroelectronics and reliability Vol. 120; pp. 1 - 8
Main Authors Marques, Ivo, Rodrigues, Cristiano, Tavares, Adriano, Pinto, Sandro, Gomes, Tiago
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.05.2021
Elsevier
Subjects
Arm
Design diversity
Dual-core lockstep
Fault tolerance
Field-programmable gate array
RISC-V
Science & Technology
Design diversity
Field-programmable gate array
RISC-V
Fault tolerance
Dual-core lockstep
Arm
Online AccessGet full text

Cover

More Information
Summary:This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores field-programmable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2021.114120