Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V
This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two...
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| Published in | Microelectronics and reliability Vol. 120; pp. 1 - 8 |
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| Main Authors | , , , , |
| Format | Journal Article |
| Language | English |
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01.05.2021
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| Abstract | This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores field-programmable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments. |
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| AbstractList | This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores field-programmable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments. This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores fieldprogrammable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments. This work has been supported by FCT - Fundação para a Ciência e a Tecnologia within the R&D Units Project Scope: UIDB/00319/2020. |
| ArticleNumber | 114120 |
| Author | Marques, Ivo Tavares, Adriano Pinto, Sandro Gomes, Tiago Rodrigues, Cristiano |
| Author_xml | – sequence: 1 givenname: Ivo surname: Marques fullname: Marques, Ivo email: ivo.marques@algoritmi.uminho.pt – sequence: 2 givenname: Cristiano surname: Rodrigues fullname: Rodrigues, Cristiano email: cristiano.rodrigues@algoritmi.uminho.pt – sequence: 3 givenname: Adriano surname: Tavares fullname: Tavares, Adriano email: atavares@dei.uminho.pt – sequence: 4 givenname: Sandro surname: Pinto fullname: Pinto, Sandro email: sandro.pinto@dei.uminho.pt – sequence: 5 givenname: Tiago surname: Gomes fullname: Gomes, Tiago email: mr.gomes@dei.uminho.pt |
| BookMark | eNqFkMtKAzEUhoMo2FZfQfICU3OSzk1cWIqXQkHwhrtwmpzR1OmkJKng2ztS3bjp6mz-7z_835Addr4jxs5AjEFAcb4ar50JPlA7lkLCGGACUhywAVSlzOoJvB6ygRCyyGQJk2M2jHElhCgFwIAtFt58ZC8XfMrfKVHwb9SR30be4LZNPPmWAnaGOAbz7hKZtA3ElxjJct_xaVhz7Cx_mD_OspcTdtRgG-n0947Y88310-wuW9zfzmfTRWZUlaesyEsh86WyytRqqbCsVYnYVFVpcwEEVa0MVkuqsaiFFU2OViHYBjAXFrFUI3a56-1nxxio0cYlTM53KaBrNQj9Y0av9J8Z_WNG78z0ePEP3wS3xvC1H-Q7MBjEjQ706WLCqKGSUldQqEkfudpFqN__6SjoaBz1Aq0LvTxtvdv35RsHSY4Z |
| CitedBy_id | crossref_primary_10_15803_ijnc_12_2_387 crossref_primary_10_1109_ACCESS_2024_3425579 crossref_primary_10_3390_electronics11050766 crossref_primary_10_1109_TNS_2024_3406021 crossref_primary_10_3390_rs13183606 crossref_primary_10_54097_fcis_v4i2_10210 crossref_primary_10_1016_j_micpro_2024_105021 |
| Cites_doi | 10.1109/ICCES.2006.320462 10.1109/TNS.2018.2852606 10.1109/MM.2005.104 10.1109/TNS.2009.2013237 10.1109/CADS.2012.6316430 10.1109/TC.2012.55 10.1109/IECON.2013.6699483 10.1109/MICRO.2018.00065 10.1109/TDMR.2005.853449 10.1109/DSN.2018.00044 10.1109/23.903784 10.1109/TC.1976.1674598 10.1109/TDSC.2004.2 10.1109/TCST.2009.2026285 10.1109/RTAS.2019.00032 10.3182/20120403-3-DE-3010.00005 10.1109/REDW.2015.7336716 10.1109/24.914545 10.1145/2935748 10.1109/ICoCS.2015.7483287 10.1109/TNS.2020.3033188 10.1109/23.556861 10.1145/1435458.1435461 10.1109/TC.2017.2737996 10.1109/DSN-W.2016.57 10.1109/ASSCC.2017.8240279 |
| ContentType | Journal Article |
| Copyright | 2021 Elsevier Ltd |
| Copyright_xml | – notice: 2021 Elsevier Ltd |
| DBID | RCLKO AAYXX CITATION |
| DOI | 10.1016/j.microrel.2021.114120 |
| DatabaseName | RCAAP open access repository CrossRef |
| DatabaseTitle | CrossRef |
| DatabaseTitleList | |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| DissertationSchool | Universidade do Minho |
| EISSN | 1872-941X |
| EndPage | 8 |
| ExternalDocumentID | 10_1016_j_microrel_2021_114120 1822_81634 S002627142100086X |
| GrantInformation_xml | – fundername: FCT grantid: UIDB/00319/2020 funderid: https://doi.org/10.13039/501100001871 |
| GroupedDBID | --K --M .DC .~1 0R~ 123 1B1 1~. 1~5 29M 4.4 457 4G. 5VS 7-5 71M 8P~ 9JN AABNK AABXZ AACTN AAEDT AAEDW AAEPC AAIAV AAIKJ AAKOC AALRI AAOAW AAQFI AAQXK AAXUO AAYFN ABBOA ABFNM ABFRF ABJNI ABMAC ABXDB ABXRA ABYKQ ACDAQ ACGFS ACNNM ACRLP ACZNC ADBBV ADEZE ADJOM ADMUD ADTZH AEBSH AECPX AEFWE AEKER AENEX AEZYN AFKWA AFRZQ AFTJW AGHFR AGUBO AGYEJ AHHHB AHJVU AHZHX AIALX AIEXJ AIKHN AITUG AJBFU AJOXV ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ AOUOD AXJTR AZFZN BJAXD BKOJK BLXMC CS3 DU5 EBS EFJIC EFLBG EJD EO8 EO9 EP2 EP3 F5P FDB FEDTE FGOYB FIRID FNPLU FYGXN G-2 G-Q GBLVA GBOLZ HVGLF HZ~ IHE J1W JJJVA KOM LY7 M41 MAGPM MO0 N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. Q38 R2- RIG RNS ROL RPZ RXW SDF SDG SES SET SEW SPC SPCBC SPD SSM SST SSV SSZ T5K T9H TAE UHS UNMZH WUQ XOL ZMT ~G- AATTM AAXKI AAYWO ACVFH ADCNI AEIPS AEUPX AFPUW AFXIZ AGCQF AGRNS AIGII AIIUN AKBMS AKRWK AKYEP ANKPU APXCP BNPGV EFKBS RCLKO AAYXX ABWVN ACRPL ADNMO AFJKZ AGQPQ CITATION SSH |
| ID | FETCH-LOGICAL-c385t-657025b3d3c93b3a7937aaf887d501e1893ca8be9a690d0f5ad3a1df1a50daa73 |
| IEDL.DBID | .~1 |
| ISSN | 0026-2714 |
| IngestDate | Tue Jul 01 01:27:35 EDT 2025 Thu Apr 24 23:08:22 EDT 2025 Fri Aug 01 16:33:02 EDT 2025 Fri Feb 23 02:41:16 EST 2024 |
| IsDoiOpenAccess | true |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Keywords | Design diversity Field-programmable gate array RISC-V Fault tolerance Dual-core lockstep Arm |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c385t-657025b3d3c93b3a7937aaf887d501e1893ca8be9a690d0f5ad3a1df1a50daa73 |
| OpenAccessLink | http://hdl.handle.net/1822/81634 |
| PageCount | 8 |
| ParticipantIDs | crossref_citationtrail_10_1016_j_microrel_2021_114120 crossref_primary_10_1016_j_microrel_2021_114120 rcaap_revistas_1822_81634 elsevier_sciencedirect_doi_10_1016_j_microrel_2021_114120 |
| ProviderPackageCode | CITATION AAYXX |
| PublicationCentury | 2000 |
| PublicationDate | 2021-05-01 |
| PublicationDateYYYYMMDD | 2021-05-01 |
| PublicationDate_xml | – month: 05 year: 2021 text: 2021-05-01 day: 01 |
| PublicationDecade | 2020 |
| PublicationTitle | Microelectronics and reliability |
| PublicationYear | 2021 |
| Publisher | Elsevier Ltd Elsevier |
| Publisher_xml | – name: Elsevier Ltd – name: Elsevier |
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| SSID | ssj0007011 |
| Score | 2.352125 |
| Snippet | This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset... |
| SourceID | crossref rcaap elsevier |
| SourceType | Enrichment Source Index Database Publisher |
| StartPage | 1 |
| SubjectTerms | Arm Design diversity Dual-core lockstep Fault tolerance Field-programmable gate array RISC-V Science & Technology |
| Title | Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V |
| URI | https://dx.doi.org/10.1016/j.microrel.2021.114120 http://hdl.handle.net/1822/81634 |
| Volume | 120 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwpV1LT8JAEN4QuOjB-Iz4IHvwWmC7Xdp6I0QCihxUCLfNtLuNEGgJlqu_3Z0-FBMTDh7bdDbN7GT2m-w38xFyp7QDrh2iaAbXlsPBswJfKAuEKcaCwPXDTCXiedwZTJzHmZhVSK_shUFaZZH785yeZeviTavwZms9n2OPr92xXebYLAPmM-xgd1yM8ubnD83DbbNcNc_uWPj1TpfworlC0ttG4xWEzXBsLkPd778PqNomBFjvHD79Y3JUoEbazX_shFR0fEoOd2YJnpHRyGQ2a3pPu_QdKS6JiQxtynoawXaZ0jRZatTQ0HT36oDiIaZoEpulVxRiRV-Grz1rek4m_Ye33sAqpBKskHsizQgstgi44qHPAw449Q4gMhlEiTbTzKCSELxA-2CqYdWOBCgOTEXM7IkCcPkFqcZJrC8JZdwDhQIcHkSOGwH4OAItitpaaAMGO3UiSv_IsJgjjnIWS1kSxhay9KtEv8rcr3XS-rZb55M09lr4pfvlr5iQJt3vta1n-yWRLG1w9oc0hZQtPQM_nat_rHtNDvAppzzekGq62epbA0vSoJHFXYPUusOnwfgLWCnf5g |
| linkProvider | Elsevier |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV1Lb9QwEB6V9gAcUHmpCwV8gGO6azveJEg9VC3VLt32AG21NzOJHdFqm6x2s0Jc-FP8QWbygEVC6gH1mshW8nk8D_nzfABvnQ8xUhmLZmgfhBrjIE2MC9BQMZamUZLVKhGnZ8PRRfhxaqYb8LO7C8O0ytb3Nz699tbtk36LZn9-dcV3fNVQRTJUsk7Mpy2z8sR__0Z123J_fESL_E6p4w_nh6OglRYIMh2bqiZ8KJNqp7NEpxq5SxxiTjvOmYH0kqJ4hnHqE6Tq0Q1yg06jdLmkf3CIkaZ578FWSO6CZRP2fvzhlUQD2cj0qWHAn7d2Lfl674ZZdgvPZx5Kcp9eyULj_46IW4sMcb4W7Y634VGbpoqDBonHsOGLJ_BwrXnhU5hMyJUGl-_FgfjKnJqSTNGXq6XIcTWrRFXOPIt2eLF-ViE4ajpRFjT1jcDCiU_jz4fB5TO4uBMAn8NmURZ-B4TUMTpW_IgxD6McMeGea3k-8MZT9jnsgenwsVnbuJz1M2a2Y6hd2w5Xy7jaBtce9H-PmzetO24dkXTw27-M0FJ8uXVsr14vy-xsSuyXlio3ZWPKd8MX_zHvG7g_Oj-d2Mn47OQlPOA3Dd9yFzarxcq_opyoSl_XNijgy10b_S94ZhwN |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Lock-V%3A+A+heterogeneous+fault+tolerance+architecture+based+on+Arm+and+RISC-V&rft.jtitle=Microelectronics+and+reliability&rft.au=Marques%2C+Ivo&rft.au=Rodrigues%2C+Cristiano&rft.au=Tavares%2C+Adriano&rft.au=Pinto%2C+Sandro&rft.date=2021-05-01&rft.pub=Elsevier+Ltd&rft.issn=0026-2714&rft.eissn=1872-941X&rft.volume=120&rft_id=info:doi/10.1016%2Fj.microrel.2021.114120&rft.externalDocID=S002627142100086X |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0026-2714&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0026-2714&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0026-2714&client=summon |