A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees

• Published in: IEEE journal of solid-state circuits Vol. 44; no. 6; pp. 1709 - 1720
• Main Authors: Shahramian, S., Voinigescu, S.P., Carusone, A.C.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.06.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Active clock distribution; active data distribution; Amplifiers; analog to digital converter (ADC); Applied sciences; Bandwidth; BiCMOS amplifiers; BiCMOS integrated circuits; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clocks; Comparators; Consumption; Degradation; digital to analog converter (DAC); DSP-based equalizers; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; flash data converters; Frequency conversion; Germanium silicon alloys; Integrated circuits; Integrated circuits by function (including memories and processors); mm-wave data converters; Preserves; Sampling; Sampling methods; Semiconductor device measurement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SiGe BiCMOS HBT; Signal convertors; Silicon germanides; Silicon germanium; Studies; Testing; track and hold amplifier (THA); transimpedance amplifier (TIA); Trees; Performance evaluation; transimpedance amplifier (TIA); Sample and hold circuit; Thermometer; flash data converters; active data distribution; digital to analog converter (DAC); Equalizer; Clock; DSP-based equalizers; Non linear phenomenon; BiCMOS technology; Flash converter; AD converter; Coding; Time converter; Delay time; Comparator circuit; Heterojunction bipolar transistors; BiCMOS amplifiers; Semiconductor alloys; Operational amplifier; analog to digital converter (ADC); SiGe BiCMOS HBT; Spurious free dynamic range; mm-wave data converters; DA converter; Mismatching; Sampling frequency; Active clock distribution; Data path; Integrated circuit; Digital signal processor; track and hold amplifier (THA)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2020657

This paper presents a 35-GS/s, 4-bit flash ADC-DAC with active data and clock distribution trees. At mm-wave clock frequencies, skew due to mismatch in the clock and data distribution paths is a significant challenge for both flash and time-interleaved converter architectures. A full-rate front-end track and hold amplifier (THA) may be used to reduce the effect of skew. However, it is found that the THA output must then be distributed to the comparators with a bandwidth greater than the sampling frequency in order to preserve the flat regions of the track and hold waveform. Instead, if the data and clock distribution have very low skew, the THA can be omitted thus obviating the associated nonlinearities and resulting in improved performance. In this work, a tree of fully symmetric and linear BiCMOS buffers, called a ldquodata treerdquo, distributes the input to the comparator bank with a measured 3-dB bandwidth of 16 GHz. The data tree is integrated into a complete 4-bit ADC including a full-rate input THA that can be disabled and a 4-bit thermometer-code DAC for testing purposes. The chip occupies 2.5 mm times 3.2 mm including pads and is implemented in 0.18 mum SiGe BiCMOS technology. The ADC consumes 4.5 W from a 3.3 V supply while the DAC operates from a 5 V supply and consumes 0.5 W. The ADC has 3.7 ENOB with a 3-dB effective resolution bandwidth of 8 GHz and a full-scale differential input range of 0.24 V pp . With the THA enabled, the performance degrades rapidly beyond 8 GHz to less than 1-bit, but with the THA disabled, the ENOB remains better than 3-bits for inputs up to 11 GHz with an SFDR of better than 26 dB.