A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array

A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of tem...

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Bibliographic Details
Published inJournal of instrumentation Vol. 7; no. 2; p. C02004
Main Authors Ugur, C, Bayer, E, Kurz, N, Traxler, M
Format Journal Article
LanguageEnglish
Published 01.02.2012
Subjects
Calibration
Channels
Clocks
Coarsening
Converters
Field programmable gate arrays
Instrumentation
Mathematical analysis
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Summary:A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. The time resolution of channels are calculated for 1 clock cycle and a minimum of 10.3 ps RMS on two channels, yielding 7.3 ps RMS (10.3 ps/ square root 2) on a single channel is achieved.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/7/02/C02004