An efficient architecture for adaptive deblocking filter of H.264/AVC video coding

This paper proposes an efficient hardware architecture to accelerate adaptive deblocking filter of H.264/A VC video coding. Compact data access unit, line-of-pixel (LOP) is defined in this paper. Line-of-pixel and build-in data buffer are employed to simplify data exchange between deblocking filter...

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Bibliographic Details
Published inIEEE transactions on consumer electronics Vol. 50; no. 1; pp. 292 - 296
Main Authors Sima, Miao, Zhou, Yuanhua, Zhang, Wei
Format Journal Article
LanguageEnglish
Published New York IEEE 01.02.2004
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Acceleration
Adaptive filters
Automatic voltage control
Codecs
Computer buffers
Hardware
Kernel
Process design
Video coding
Virtual colonoscopy
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Summary:This paper proposes an efficient hardware architecture to accelerate adaptive deblocking filter of H.264/A VC video coding. Compact data access unit, line-of-pixel (LOP) is defined in this paper. Line-of-pixel and build-in data buffer are employed to simplify data exchange between deblocking filter and outside data memory. Edge filter, which is designed to process each group of pixels on both sides of one edge, is kernel of deblocking filter. It is implemented in multiple parallel pipelines to increase efficiency. By carefully design, the proposed deblocking filter can be embedded in general-purpose processor or DSP to support special instructions for acceleration of software codec. This filter also can be used to full hardware H. 264/A VC codec.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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content type line 23
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2004.1277876