Micropreemption synthesis: an enabling mechanism for multitask VLSI systems

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 25; no. 1; pp. 19 - 30
• Main Authors: Kyosun Kim, Karri, R., Potkonjak, M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Asynchronous transfer mode; Clocks; Context switch overhead; critical section; Delay; Digital signal processing; Integrated circuits; Jitter; micropreemption; multitask VLSI systems; Partitioning; Preemption; preemption latency; Preserves; Random access memory; Real time systems; Registers; rolling forward; Switches; Synthesis; Tasks; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.852668

Task preemption is a critical enabling mechanism in multitask very large scale integration (VLSI) systems. On preemption, data in the register files must be preserved for the task to be resumed. This entails extra memory to preserve the context and additional clock cycles to save and restore the context. In this paper, techniques and algorithms to incorporate micropreemption constraints during multitask VLSI system synthesis are presented. Specifically, algorithms to insert and refine preemption points in scheduled task graphs subject to preemption latency constraints, techniques to minimize the context switch overhead by considering the dedicated registers required to save the state of a task on preemption and the shared registers required to save the remaining values in the tasks, and a controller-based scheme to preclude the preemption-related performance degradation by: 1) partitioning the states of a task into critical sections; 2) executing the critical sections atomically; and 3) preserving atomicity by rolling forward to the end of the critical sections on preemption have been developed. The effectiveness of all approaches, algorithms, and software implementations is demonstrated on real examples. Validation of all the results is complete in the sense that functional simulation is conducted to complete layout implementation.