Comparison of two designs for the multifunction vehicle bus

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 25; no. 5; pp. 797 - 805
• Main Authors: Jimenez, J., Martin, J.L., Zuloaga, A., Bidarte, U., Arias, J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Buses (vehicles); Circuit synthesis; Consumer electronics; Decoders; Decoding; Design engineering; Design methodology; Devices; Digital systems; Fabrics; Field programmable gate arrays; Logic arrays; logic design; Methodology; Programmable logic arrays; rail transportation electronics; Routing; Synthesis; train communication network (TCN); Vehicles
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.855925

In this paper, two designs for the decoder of the multifunction vehicle bus (MVB) are compared. The first one follows a bottom-up methodology and the second one has been created in a top-down style. Although this latter methodology is more systematic and easy to automate, it results in a lower performance. In the case of the MVB decoder, the ratio of bottom-up performance to the top-down one ranges from 1.90 to 4.12, depending on the synthesis tool and the device. Selecting as reference the tool and field-programmable gate array (FPGA) that use the fewest logical elements, the bottom-up design can work 2.3 times faster than the top-down one, after two and three iterations for the physical implementation, respectively. In both cases, the circuit has been synthesized on a Virtex-E XCV3200E of Xilinx by Xilinx Synthesis Tool (XST), so that there has been no shortage of physical resources. Therefore, for a particular pair of synthesis tool and device, the final implementation is determined by the design style and not by a hard placement and routing in a hostile fabric. After synthesis, the top-down design was 23.37% larger than the bottom-up design, so the results are not as poor as expected from a nonstructured design; however, this percentage, which is always positive, depends very strongly upon the particular synthesis tool and FPGA. In addition, both descriptions have been completely implemented in a similar CPU time (even the top-down one slightly more quickly, at the first attempt). So the top-down design style is a good candidate to produce circuits in a short time to market (in this case 28% lower), although synthesis tools must be improved in order to increase the performance.