A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

• Published in: IEEE journal of solid-state circuits Vol. 40; no. 1; pp. 245 - 253
• Main Authors: Noda, H., Inoue, K., Kuroiwa, M., Igaue, F., Yamamoto, K., Mattausch, H.J., Koide, T., Amo, A., Hachisuka, A., Soeda, S., Hayashi, I., Morishita, F., Dosaka, K., Arimoto, K., Fujishima, K., Anami, K., Yoshihara, T.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.01.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Architecture; Arrays; CADCAM; Chip formation; Chips; Circuits; CMOS memory integrated circuits; Computer aided manufacturing; Costs; Design. Technologies. Operation analysis. Testing; Dynamics; Electronics; embedded DRAM; Exact sciences and technology; Integrated circuit yield; Integrated circuits; Integrated circuits by function (including memories and processors); Large-scale systems; network; Power dissipation; Random access memory; Redundancy; Searching; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; ternary CAM; Yield estimation; Cell structure; High performance; Dynamic characteristic; Random access memory; Network architecture; CMOS memory circuits; Pipeline processing; network; Low voltage; Energy dissipation; Integrated circuit; Integrated memory circuits; ternary CAM; embedded DRAM; CMOS integrated circuits; Large scale; Low-power electronics; CMOS memory integrated circuits; Dynamic random access memory
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.838016

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.