Analysis and methodology for multiple-fault diagnosis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 25; no. 3; pp. 558 - 575
• Main Authors: Zhiyuan Wang, Marek-Sadowska, M., Tsai, K.-H., Rajski, J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Central Processing Unit; Central processing units; Circuit faults; Circuit simulation; Circuit testing; Circuits; Computer aided design; Design engineering; Diagnostic systems; Failure analysis; Faults; Linear approximation; Manufacturing industries; Manufacturing processes; Methodology; Partitioning algorithms; Pattern analysis
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.854624

In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time.