A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

• Published in: IEEE journal of solid-state circuits Vol. 40; no. 1; pp. 52 - 59
• Main Authors: McIntyre, H., Wendell, D., Lin, K.J., Kaushik, P., Seshadri, S., Wang, A., Sundararaman, V., Ping Wang, Song Kim, Hsu, W.-J., Hee-Choul Park, Levinsky, G., Jiejun Lu, Chirania, M., Heald, R., Lazar, P., Dharmasena, S.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.01.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Applied sciences; Arrays; Cache memories; Circuit properties; Circuits; Clocks; CMOS; CMOS process; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Flexible printed circuits; integrated circuit design; Integrated circuits; Integrated circuits by function (including memories and processors); manufacturability; memory architectures; Microprocessors; Operational amplifiers; random access memories; Random access memory; Reduced instruction set computing; Repeaters; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SPARC; Static random access memory; static sense amplifier; Time measurements; Timing; Transistors; Performance evaluation; Static random access memory; SPARC; Cache memory; Random access memory; Cache memories; static sense amplifier; Integrated circuit design; 64 bit Processor; memory architectures; Transistor; Amplifier; Clock; Combiner circuit; RISC processor; Power combiners; Complementary MOS technology; Integrated circuit; Repeater; random access memories; Microprocessor; microprocessors; manufacturability
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.838017

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.