A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With -75 dBc Single-Tone Sensitivity at 100 kHz Offset

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 12; pp. 2758 - 2765
• Main Authors: Khalil, W., Bakkaloglu, B., Kiaei, S.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.12.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Built-in self-test; Built-in self-test (BIST); Calibration; Carrier frequencies; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Clocks; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Equivalence; Exact sciences and technology; Frequency; Integrated circuit measurements; Integrated circuits; Jitter; Measurement techniques; Modules; Offsets; Oscillators, resonators, synthetizers; Phase locked loops; Phase measurement; phase noise; phase-locked loops (PLLs); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Spectra; Testing, measurement, noise and reliability; Time measurement; Phase noise; Phase measurement; Low noise circuit; Phase fluctuation; Mixer; Jitter; Base band; Clock; Noise measurement; Voltage control; Discriminator; Frequency synthesizer; Phase locked loop; Noise spectrum; Low voltage; Time domain method; Built-in self-test (BIST); Selfcalibration; phase-locked loops (PLLs); Measurement method; Monolithic integrated circuit; Delay line; Built in self test
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2007.908689

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.