Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 25; no. 7; pp. 1392 - 1400
• Main Authors: Shi, C.-J.R., Tian, M.W., Guoyong Shi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog circuits; Analog testing; Approximation; Circuit faults; Circuit simulation; Circuit testing; Circuits; Computational modeling; Computer simulation; dc fault simulation; Direct current; Electrical fault detection; Failure analysis; fault coverage; Fault detection; fault ordering; Faults; first-order approximation; Iterative methods; Mathematical models; Newton-Raphson iteration; Nonlinearity; Predictive models; simulation continuation; System testing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.855884

Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By one-step relaxation, only one Newton-Raphson iteration is performed for each faulty circuit with the dc solution of the good circuit as the initial point, and the approximate solution is used for detecting the fault. The paper shows experimentally and justifies theoretically that approximate dc fault simulation by one-step relaxation can accomplish almost the same fault coverage as exact dc fault simulation. Exact dc fault simulation by adaptive simulation continuation is first to order faulty circuits based on the results of one-step relaxation, and then to use the solution of the previous faulty circuit as the initial point for the Newton-Raphson iteration of the next faulty circuit. Experiments on a set of 29 MCNC Circuit Simulation and Modeling Workshop benchmark circuits show that exact dc fault simulation by adaptive simulation continuation can achieve an average speedup of 4.4 and as high as 15 over traditional stand-alone fault simulation